1. Field of the Invention
The present invention relates to a non-volatile memory circuit capable of electrical writing and reading.
2. Description of the Related Art
There is known a semiconductor integrated circuit including a bleeder resistor circuit capable of trimming a resistance value by a memory instead of a fuse. Hitherto, the bleeder resistance is adjusted by a method of mechanically cutting the fuse formed in parallel to the bleeder resistor with use of laser light or the like. The trimming of the bleeder resistor can accordingly be performed only before assembling a package. The use of a memory for trimming the bleeder resistor, on the other hand, enables electrical trimming even after the assembly. The following two typical benefits are obtained.
1. Customers' requests for quick delivery can be accommodated because the trimming is carried out for the bleeder resistor in the package and any further processing is unnecessary before shipment.
2. High precision can be achieved because the trimming covers package-related shift, which is electrical characteristics fluctuation that occurs due to stress in assembling the package.
In general, once the bleeder resistor is trimmed, there is no need to rewrite thereafter information represented by stored electrical charges. As a trimming memory, a one-time programmable (OTP) memory using an ultraviolet erasable, non-volatile erasable programmable read only memory (EPROM) can accordingly be used.
As a related-art ultraviolet erasable non-volatile EPROM, a non-volatile EPROM designed to write electric charges as information with use of hot carriers is known. The structure of the related-art non-volatile EPROM designed to write information with the use of hot carriers is exemplified with reference to FIG. 4.
A P-type well 16 is formed along one principal surface of a P-type semiconductor substrate 15 in which an element isolation region 17 is selectively formed. In the P-type well 16, impurities having N-type conductivity are heavily diffused to form a source region 18 and a drain region 19. On the semiconductor substrate in which the source region 18 and the drain region 19 are formed, a floating gate 21 is formed through intermediation of a gate oxide film 20. On the floating gate 21, a control gate 23 is formed through intermediation of a second insulating film 22. The related-art non-volatile EPROM is configured in this way. The structure of electrode wiring and other members to be formed in subsequent processes (metal wiring and protective film) is the same as that in a commonly used semiconductor device, and hence its detailed description is omitted.
Next, a description is given of an operation method of the related-art non-volatile EPROM.
In writing data, a voltage is applied between the source and the drain and to the control gate so as to generate hot carriers. Then, hot electrons as hot carriers are injected into the floating gate, to thereby shift a threshold voltage. Each state before and after the threshold voltage shift is associated with “0” or “1” of digital information.
In reading data, a potential is applied between the source and the drain, and the magnitude of a current corresponding to the threshold that differs depending on the presence or absence of writing is monitored, to thereby make a determination of “0” or “1”.
In the related-art non-volatile EPROM, however, because the potential is applied between the source and the drain and the current flows in reading data, electrons move between the source and the drain so that a part of the electrons in slight amount become hot carriers to be injected into the floating gate, resulting in causing a threshold shift. Accordingly, if the reading operation is repeated, the problem of erroneous writing in which data is rewritten occurs. It is thus required for the related-art non-volatile EPROM to reduce the threshold shift due to erroneous writing.
In Japanese Published Patent Application No. 2001-257324, the following method is employed to reduce the threshold shift due to erroneous writing. FIG. 5 illustrates a schematic diagram of the invention described in Japanese Published Patent Application No. 2001-257324. A semiconductor integrated circuit of Japanese Published Patent Application No. 2001-257324 includes non-volatile memories (PM1 and PM2 of FIG. 5) having different threshold voltages and two read transistors (DM1 and DM2 of FIG. 5) having gate voltages corresponding to respective voltage of the floating gates of the two non-volatile memories and being capable of taking a state depending on the quantity of electric charges stored in the respective non-volatile memories. The two read transistors can prevent the current flow through the non-volatile memories in read mode, thereby preventing the threshold shift due to erroneous writing.
In the method described in Japanese Published Patent Application No. 2001-257324, however, although the threshold shift due to erroneous writing may be prevented, the two non-volatile semiconductor memories having different thresholds as well as the two read transistors are necessary for each memory cell. As a result, the area of the memory cell becomes larger to be disadvantageous also in terms of cost.